Efficiently Tolerating Timing Violations in Pipelined Microprocessors

Autor:	Sanghamitra Roy, Koushik Chakraborty, Dean Michael Ancajas, Brennan Cozzens
Přispěvatelé:	Association for Computing Machinery
Rok vydání:	2013
Předmět:	Engineering business.industry Computer science Embedded system Instruction scheduling Instruction Scheduling Systems design Fault tolerance Electrical and Computer Engineering business Path Sensitization Timing Faults
Zdroj:	Electrical and Computer Engineering Faculty Publications DAC
Popis:	Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the performance overhead of tolerating these faults. In this paper, we explore several techniques for optimizing instruction scheduling in an Out-of-Order pipeline, exploiting this new perspective in robust system design. Compared to recently proposed stall based techniques for tolerating predictabletiming violations, we demonstrate a massive reduction in performance overhead, while supporting correct execution in faulty environments (64-97% across different benchmarks). Copyright © 2013 ACM.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::854b37f55280896e79d4eadcd1a74066 https://digitalcommons.usu.edu/ece_facpub/258 Zobrazit plný text záznamu