Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating
| Autor: | D. Lizzit, Francesco Driussi, David Esseni, Pierpaolo Palestri, Oves Badami |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
FinFETs
Computer science stacked-nanowire FETs 02 engineering and technology 01 natural sciences surface roughness scattering law.invention Parasitic capacitance law 0103 physical sciences MOSFET Electronic Electronic engineering Surface roughness Point (geometry) nanowire FETs Optical and Magnetic Materials Electrical and Electronic Engineering 010302 applied physics Transistor self-heating Benchmarking 021001 nanoscience & nanotechnology Boltzmann equation Electronic Optical and Magnetic Materials 0210 nano-technology Focus (optics) |
| Zdroj: | IEEE Transactions on Electron Devices. 65:3646-3653 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2018.2857509 |
| Popis: | Tremendous improvements in the fabrication technology have allowed to scale the physical dimensions of the transistors and also to develop different promising 3-D architectures that may allow continuing Moore’s law. In this paper, we perform a comparative delay analysis of different 3-D device architectures and study the impact of surface roughness and self-heating on the on-current using a comprehensive in-house simulation framework comprising Schrodinger, Poisson, and Boltzmann transport equation solvers and comprising relevant scattering mechanisms and self-heating. Our results highlight that parasitic capacitance can alter the relative ranking of the architectures from delay point of view. We demonstrate that surface roughness can cause architecture and material-dependent current degradation, and hence, it is necessary to account for it in simulation-based benchmarking different architectures. |
| Databáze: | OpenAIRE |
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