FPGA-controlled PCBA power-on self-test using processor's debug features
| Autor: | Erwing R. Sanchez, M. Sonza Reorda, J. Perez Acle, Anton Tsertov, Boyang Du |
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| Rok vydání: | 2016 |
| Předmět: |
Risk
Engineering media_common.quotation_subject Functional approach 02 engineering and technology 01 natural sciences Software 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Observability Electrical and Electronic Engineering Field-programmable gate array media_common 010302 applied physics Forcing (recursion theory) business.industry Hardware and Architecture Safety Risk Reliability and Quality 020202 computer hardware & architecture Debugging Reliability and Quality Embedded system Fault coverage Safety business Power-on self-test |
| Zdroj: | DDECS |
| DOI: | 10.1109/ddecs.2016.7482458 |
| Popis: | When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory. |
| Databáze: | OpenAIRE |
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