A WiMAX turbo decoder with tailbiting BIP architecture

Autor:	Naoto Miyamoto, Takashi Ito, Koji Kotani, Hiroaki Arai, Hisanori Fujisawa
Rok vydání:	2009
Předmět:	biology business.industry Computer science Pipeline (computing) Turbo Hardware_PERFORMANCEANDRELIABILITY Data_CODINGANDINFORMATIONTHEORY Chip biology.organism_classification WiMAX CMOS Turbo code Electronic engineering Bit error rate Trellis modulation business Computer hardware
Zdroj:	2009 IEEE Asian Solid-State Circuits Conference.
DOI:	10.1109/asscc.2009.5357175
Popis:	In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is increased. Instead of the SW, we combined the tailbiting method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::815d69edb78c7228f2b266a68770ebf4 https://doi.org/10.1109/asscc.2009.5357175 Zobrazit plný text záznamu