| Autor: |
Ranganathan Nagarajan |
| Přispěvatelé: |
Pey Kin Leong, School of Electrical and Electronic Engineering, A*STAR Institute of Microelectronics, Krishnamachar Prasad |
| Rok vydání: |
2019 |
| Předmět: |
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| DOI: |
10.32657/10356/41775 |
| Popis: |
Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of planar integrated circuits. This work focuses on various challenges associated with deep reactive ion etching technology for realizing through silicon interconnection for 3D Microsystems application. In the first part of the thesis, stress simulation studies were done on TSV structures of various via geometries and shapes to determine the regions of high stress due to CTE mismatch. It was determined that the top and bottom of the vias and the surrounding materials experience maximum mechanical stress. It was also found that the stress is concentrated in the sharp peaks and valleys of the scallops formed by Bosch etch process. A test vehicle was designed and fabricated by copper damascene process with various geometries and barrier structures to experimentally study the effect of sidewall scallops on electrical leakage between adjacent TSV structures. It was shown that the leakage current can be reduced by about nearly 3 orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall for the initial few microns of the depth of the via by using a non-Bosch etch process. This study has shown that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, for vertical TSV etch application by tailoring a short first etch step with smooth sidewall. DOCTOR OF PHILOSOPHY (EEE) |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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