Actors with stretchable access patterns

Autor: Stéphane Domas, Ke Du, Michel Lenczner
Přispěvatelé: Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies (UMR 6174) (FEMTO-ST), Université de Technologie de Belfort-Montbeliard (UTBM)-Ecole Nationale Supérieure de Mécanique et des Microtechniques (ENSMM)-Université de Franche-Comté (UFC), Université Bourgogne Franche-Comté [COMUE] (UBFC)-Université Bourgogne Franche-Comté [COMUE] (UBFC)-Centre National de la Recherche Scientifique (CNRS)
Rok vydání: 2019
Předmět:
[SPI.OTHER]Engineering Sciences [physics]/Other
Data stream
Correctness
Theoretical computer science
Computer science
Dataflow
[INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
02 engineering and technology
[INFO.INFO-IU]Computer Science [cs]/Ubiquitous Computing
[INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]
VHDL
0202 electrical engineering
electronic engineering
information engineering
Electrical and Electronic Engineering
Static data
computer.programming_language
020208 electrical & electronic engineering
[INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation
Graph
020202 computer hardware & architecture
Fpga design
[INFO.INFO-MA]Computer Science [cs]/Multiagent Systems [cs.MA]
Hardware and Architecture
[INFO.INFO-ET]Computer Science [cs]/Emerging Technologies [cs.ET]
[INFO.INFO-DC]Computer Science [cs]/Distributed
Parallel
and Cluster Computing [cs.DC]
computer
Software
Zdroj: Integration
Integration, 2019, 66, pp.44-59. ⟨10.1016/j.vlsi.2019.01.001⟩
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2019.01.001
Popis: International audience; In this article, we propose a new framework based on dataflow graphs to abstract and analyze designs for hardware architectures. It is called Actors with Stretchable Access Patterns (ASAP). It can overcome some limitations of all Static Data Flow (SDF) based models like mandatory buffering between actors. This article details the fundamental contributions of ASAP. Firstly, it gives the definition of actors and their different patterns. It also illustrates the link between these notions and components written in VHDL through several examples. Secondly, it presents the main algorithms to check if a graph processes an input data stream correctly, which is called compatibility checking. Thirdly, it summarizes the principles of graph modification to enforce this correctness in case of some blocks are declared incompatible. Finally, it briefly describes our EDA tool called BlAsT which integrates the above principles, before presenting an application on a realistic FPGA design. It shows that ASAP overwhelms other models in terms of resources saving without any impact on the global latency. It also points out the ability of BlAsT to compute and to propose graph modifications and to generate the VHDL code of the whole design.
Databáze: OpenAIRE
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