Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves
| Autor: | Nicolas Estibals, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez, Jean-Luc Beuchat |
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| Přispěvatelé: | Laboratory of Cryptography and Information Security (LCIS), Université de Tsukuba = University of Tsukuba, Cryptology, Arithmetic: Hardware and Software (CARAMEL), Inria Nancy - Grand Est, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Department of Algorithms, Computation, Image and Geometry (LORIA - ALGO), Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Centre National de la Recherche Scientifique (CNRS)-Université de Lorraine (UL)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Lorraine (UL)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Centre National de la Recherche Scientifique (CNRS)-Université de Lorraine (UL)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Lorraine (UL), Centro de Investigacion y de Estudios Avanzados del Instituto Politécnico Nacional (CINVESTAV), Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lorraine (UL)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lorraine (UL)-Centre National de la Recherche Scientifique (CNRS)-Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lorraine (UL)-Centre National de la Recherche Scientifique (CNRS)-Université de Lorraine (UL)-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: |
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
Exponentiation Coprocessor [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic Karatsuba algorithm 02 engineering and technology Supersingular elliptic curve Field arithmetic 020202 computer hardware & architecture Theoretical Computer Science [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR] Computational Theory and Mathematics Hardware and Architecture Pairing 0202 electrical engineering electronic engineering information engineering Tate pairing 020201 artificial intelligence & image processing Finite field arithmetic Arithmetic Hardware_ARITHMETICANDLOGICSTRUCTURES Software Mathematics |
| Zdroj: | IEEE Transactions on Computers IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2011, Special Section on Computer Arithmetic, 60 (2), pp.266-281. ⟨10.1109/TC.2010.163⟩ IEEE Transactions on Computers, 2011, Special Section on Computer Arithmetic, 60 (2), pp.266-281. ⟨10.1109/TC.2010.163⟩ |
| ISSN: | 0018-9340 |
| DOI: | 10.1109/TC.2010.163⟩ |
| Popis: | International audience; This paper is devoted to the design of fast parallel accelerators for the cryptographic $\eta_T$ pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the $\eta_T$ pairing over $\F_{2^m}$ and $\F_{3^m}$. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the $\eta_T$ pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previously published coprocessors. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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