Peak Power Estimation: A Case Study on CPU Cores
| Autor: | Patrick Girard, Paolo Bernardi, Alberto Bosio, Ernesto Sanchez, M. Sonza Reorda, Luigi Dilillo, Miroslav Valka, M. de Carvalho |
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| Přispěvatelé: | Politecnico di Torino = Polytechnic of Turin (Polito), Dipartimento di Automatica e Informatica [Torino] (DAUIN), dauin, Politecnico di Torino = Polytechnic of Turin (Polito)-Politecnico di Torino = Polytechnic of Turin (Polito), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Jazyk: | angličtina |
| Rok vydání: | 2012 |
| Předmět: |
Multi-core processor
Engineering Peak power estimation business.industry Estimation theory Real-time computing Mode (statistics) 02 engineering and technology Automatic test pattern generation 020202 computer hardware & architecture Power (physics) [SPI.TRON]Engineering Sciences [physics]/Electronics Identification (information) Functional power component Logic gate At-speed delay fault testing 0202 electrical engineering electronic engineering information engineering Power-aware testing Central processing unit business |
| Zdroj: | IEEE Asian Test Symposium IEEE Asian Test Symposium, Nov 2012, Niigata, Japan. pp.167-172, ⟨10.1109/ATS.2012.58⟩ Asian Test Symposium |
| Popis: | International audience; High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of over-consumption. Measuring power consumption is a very time consuming activity, therefore many works in the literature focused on the indirect ways to provide power consumption estimation in a fast manner. In this paper we concentrate on a similar issue, concentrating our effort on devising a fast method for the identification and estimation of the peak power produced by test patterns. In particular we provide a detailed discussion on case studies related to peak power estimation of CPU cores when executing functional patterns, the proposed method uses the gate-level description of the CPU to identify a subset of time points over the entire test pattern that are showing the most significant peak power values. The proposed methodology has been validated on two case studies synthesized in a 65nm industrial technology. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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