Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications
| Autor: | Clement Beauquier, David Duperray, Chadi Jabbour, Patricia Desgreys, Antoine Frappe, Andreas Kaiser |
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| Přispěvatelé: | STMicroelectronics [Grenoble] (ST-GRENOBLE), Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Microélectronique Silicium - IEMN (MICROELEC SI - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), Institut Polytechnique de Paris (IP Paris), Département Communications & Electronique (COMELEC), Télécom ParisTech, Circuits et Systèmes de Communication (C2S), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, no information, Laboratoire commun STMicroelectronics-IEMN T2 |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: | |
| Zdroj: | 28th IEEE International Conference on Electronics Circuits and Systems, ICECS 2021 28th IEEE International Conference on Electronics Circuits and Systems, ICECS 2021, Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665600⟩ |
| DOI: | 10.1109/ICECS53924.2021.9665600⟩ |
| Popis: | POSTER; International audience; This work presents the first 21-43 GHz CMOS analog Duty Cycle Controller (DCC) implemented in 28 nm FDSOI. The main application is millimeter wave mixers with CMOS digital signals. The proposed circuit corrects the input duty cycle with a negative feedback analog loop. Observability of the duty cycle is made through a passive low pass filter and the control is achieved by modifying the rise and fall time of the input clock signal, via backgate biasing of an inverter chain. The circuit has been validated by post layout, Monte-Carlo and corner simulations. At 28 GHz, the duty cycle correction range varies from 40 % to 55 %, and the additional power consumption introduced by the correction loop is frequency independent and is equal to 0.6 mW. |
| Databáze: | OpenAIRE |
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