Design Time Engineering of Side Channel Resistant Cipher Implementations
| Autor: | F. De Santis, Filippo Melzani, Alessandro Barenghi, Andrea Palomba, Gerardo Pelosi, Luca Breveglieri |
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| Rok vydání: | 2013 |
| Předmět: |
Engineering
cryptography business.industry power attack Cryptography security Computer security computer.software_genre Fault (power engineering) fault attack Power analysis side-channel attack hardware design Cipher Information leakage Information system Side channel attack business computer Implementation |
| DOI: | 10.4018/978-1-4666-4030-6.ch006 |
| Popis: | Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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