Real-Time Highly Accurate Dense Depth on a Power Budget Using an FPGA-CPU Hybrid SoC
| Autor: | Stuart Golodetz, Thomas Joy, Philip H. S. Torr, Oscar Rahnama, Alessio Tonioni, Tommaso Cavallari, Simon Walker, Luigi Di Stefano |
|---|---|
| Přispěvatelé: | Rahnama O., Cavallari T., Golodetz S., Tonioni A., Joy T., Di Stefano L., Walker S., Torr P.H.S. |
| Rok vydání: | 2019 |
| Předmět: |
Signal Processing (eess.SP)
FOS: Computer and information sciences depth Computer science Computer Vision and Pattern Recognition (cs.CV) Computer Science - Computer Vision and Pattern Recognition real-time Word error rate 02 engineering and technology Power budget FOS: Electrical engineering electronic engineering information engineering 0202 electrical engineering electronic engineering information engineering Leverage (statistics) Electrical Engineering and Systems Science - Signal Processing Electrical and Electronic Engineering Field-programmable gate array FPGA business.industry Heterogeneou Image and Video Processing (eess.IV) stereo Robotics Electrical Engineering and Systems Science - Image and Video Processing Chip 020202 computer hardware & architecture Computer engineering Key (cryptography) 020201 artificial intelligence & image processing Artificial intelligence Central processing unit business |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 66:773-777 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2019.2909169 |
| Popis: | Obtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as FPGAs. Whilst various stereo algorithms have been deployed on these platforms, usually cut down to better match the embedded architecture, certain key parts of the more advanced algorithms, e.g. those that rely on unpredictable access to memory or are highly iterative in nature, are difficult to deploy efficiently on FPGAs, and thus the depth quality that can be achieved is limited. In this paper, we leverage a FPGA-CPU chip to propose a novel, sophisticated, stereo approach that combines the best features of SGM and ELAS-based methods to compute highly accurate dense depth in real time. Our approach achieves an 8.7% error rate on the challenging KITTI 2015 dataset at over 50 FPS, with a power consumption of only 5W. Comment: 6 pages, 7 figures, 2 tables, journal |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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