Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures
| Autor: | K.N. Vikram, Vinita Vasudevan |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2006 |
| Předmět: |
Schedule
Partial reconfiguration Speedup Finite impulse response Computer science Integrated circuit Parallel computing Data recording law.invention law Overhead (computing) Hybrid processor architectures Computer architecture Computer software Electrical and Electronic Engineering Field-programmable gate array Data parallel tasks Control reconfiguration Field programmable gate arrays Computer hardware Dynamically reconfigurable logic (DRL) Program processors Reconfigurable computing Mapping Hardware and Architecture Hybrid system Divisible load theory Software |
| Zdroj: | IndraStra Global. |
| ISSN: | 2381-3652 |
| Popis: | Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board. � 2006 IEEE. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|