A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS
| Autor: | Hung-Yi Kuo, Chih-Hsien Chang, Chia-Chun Liao, Tsung-Hsien Tsai, Yu-Tso Lin, Robert Bogdan Staszewski, Tien-Chien Huang, Min-Shueh Yuan, Chao-Chieh Li, Hsien-Yuan Liao, Augusto Ronchini Ximenes, Chung-Ting Lu |
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| Rok vydání: | 2021 |
| Předmět: |
Wide tuning range (TR)
Phase locked loops Topology (electrical circuits) 02 engineering and technology Tuning Inductor TDC gain estimator wide tuning range (TR) Noise (electronics) Phase detector law.invention metastability compact area law 0202 electrical engineering electronic engineering information engineering Electronic engineering Inductors Oscillators All-digital phase-locked loop (ADPLL) Electrical and Electronic Engineering Clocks Jitter Physics Transformer 020208 electrical & electronic engineering Q-factor Time-to-digital converter (TDC) fractional-N Phase-locked loop Capacitor CMOS FinFET Couplings |
| Zdroj: | IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 68(5) |
| ISSN: | 1558-0806 1549-8328 |
| Popis: | In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB. |
| Databáze: | OpenAIRE |
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