Self-checking circuits versus realistic faults in very deep submicron
| Autor: | I. Alzaher-Noufal, Michael Nicolaidis, Lorena Anghel |
|---|---|
| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2000 |
| Předmět: |
Engineering
self-checking-circuits realistic-faults 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY 01 natural sciences Noise (electronics) Field (computer science) device-size Manufacturing testing 0103 physical sciences very-deep-submicron 0202 electrical engineering electronic engineering information engineering Electronic engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Spurious relationship Electronic circuit 010302 applied physics speed business.industry Self checking 020202 computer hardware & architecture Power (physics) power-supply-levels Built-in self-test PACS 85.42 IC-technologies business |
| Zdroj: | Proceedings-18th-IEEE-VLSI-Test-Symposium Proceedings-18th-IEEE-VLSI-Test-Symposium, 2000, Montreal, Que., Canada. pp.55-63, ⟨10.1109/VTEST.2000.843827⟩ VTS |
| DOI: | 10.1109/VTEST.2000.843827⟩ |
| Popis: | ISBN: 0769506135; IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result in spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result in unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies. |
| Databáze: | OpenAIRE |
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