Design Space exploration of FPGA-based accelerators with multi-level parallelism
| Autor: | Yun Liang, Smail Niar, Guanwen Zhong, Siqi Wang, Tulika Mitra, Alok Prakash |
|---|---|
| Přispěvatelé: | National University of Singapore (NUS), Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Computer science
Data parallelism Design space exploration 020208 electrical & electronic engineering Task parallelism Field programmable gate arrays 02 engineering and technology Parallel computing 020202 computer hardware & architecture Table lookup Tools Kernel Pipeline processing 0202 electrical engineering electronic engineering information engineering Leverage (statistics) [INFO]Computer Science [cs] Field-programmable gate array Nested loop join Instruction-level parallelism Estimation |
| Zdroj: | IEEE/ACM Design Automation and Test in Europe (DATE'17) IEEE/ACM Design Automation and Test in Europe (DATE'17), Mar 2017, Lausanne, Switzerland. pp.1141-1146, ⟨10.23919/DATE.2017.7927161⟩ DATE |
| Popis: | International audience; Applications containing compute-intensive kernels with nested loops can effectively leverage FPGAs to exploit fine-and coarse-grained parallelism. HLS tools used to translate these kernels from high-level languages (e.g., C/C--), however, are inefficient in exploiting multiple levels of parallelism automatically, thereby producing sub-optimal accelerators. Moreover, the large design space resulting from the various combinations of fineand coarse-grained parallelism options makes exhaustive design space exploration prohibitively time-consuming with HLS tools. Hence, we propose a rapid estimation framework, MPSeeker, to evaluate performance/area metrics of various accelerator options for an application at an early design phase. Experimental results show that MPSeeker can rapidly (in minutes) explore the complex design space and accurately estimate performance/area of various design points to identify the near-optimal (95.7% performance of the optimal on average) combination of parallelism options. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|