Chip-Level ESD Verification Using Graph-Theory Based Approach
| Autor: | Renaud Gillon, Adrijan Baric, Aarnout Wieers, Vlatko Galic |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Electrostatic discharge ESD full-chip simulations bipolar technology ESD verification graph theory ESD current paths Computer science 020206 networking & telecommunications Graph theory Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit Chip 01 natural sciences law.invention law Robustness (computer science) 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_LOGICDESIGN Voltage |
| Zdroj: | 2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE. |
| Popis: | An Electrostatic Discharge (ESD) simulation and verification flow that has been demonstrated on a real design in bipolar technology is presented in this work. The described flow can be used to verify the level of ESD robustness of integrated circuit (IC) designs. Secondly, it is possible to identify the ESD current paths between any two nodes in the design, and the flow can determine which devices will fail in the case of a catastrophic ESD event. The presented flow is based on a graph-theory Floyd-Warshall algorithm and previously defined breaking voltage (BV) models. |
| Databáze: | OpenAIRE |
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