Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency
| Autor: | Dragomir M. El Mezeni, Andreja Radosevic, Vladimir L. Petrovic |
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| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
Schedule
hardware usage efficiency TK7800-8360 Computer Networks and Communications Computer science channel coding 02 engineering and technology low-density parity-check (LDPC) codes Bit array Encoding (memory) 0202 electrical engineering electronic engineering information engineering Code (cryptography) encoder architecture Electrical and Electronic Engineering Latency (engineering) Low-density parity-check code 5G new radio circular shifter business.industry 020208 electrical & electronic engineering 020206 networking & telecommunications Parity-check matrix Hardware and Architecture Control and Systems Engineering genetic algorithm optimization Signal Processing Electronics business Encoder Computer hardware |
| Zdroj: | Electronics Volume 10 Issue 9 Electronics, Vol 10, Iss 1106, p 1106 (2021) |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics10091106 |
| Popis: | Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE. |
| Databáze: | OpenAIRE |
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