Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
| Autor: | Patrick Girard, Alberto Bosio, Luigi Dilillo, Serge Pravossoudovitch, Renan Alves Fonseca, N. Badereddine, Arnaud Virazel |
|---|---|
| Přispěvatelé: | Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Intel Mobile, Intel Mobile Communications (IMC), Intel Mobile Communications-Intel-Intel Mobile Communications-Intel, D. Gizopoulos, European Project, Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Rok vydání: | 2012 |
| Předmět: |
Core-cell
Resistive touchscreen Test Materials science Bridging (networking) business.industry 020208 electrical & electronic engineering Resistive-bridge defect Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fault modeling SRAM [SPI.TRON]Engineering Sciences [physics]/Electronics 020202 computer hardware & architecture 0202 electrical engineering electronic engineering information engineering Electronic engineering Optoelectronics Static random-access memory Electrical and Electronic Engineering business Voltage |
| Zdroj: | Journal of Electronic Testing: : Theory and Applications Journal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩ Journal of Electronic Testing Journal of Electronic Testing, Springer Verlag, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩ |
| ISSN: | 1573-0727 0923-8174 |
| DOI: | 10.1007/s10836-012-5291-6 |
| Popis: | International audience; We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes. |
| Databáze: | OpenAIRE |
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