SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management
| Autor: | Roghayeh Saeidi, David Bol, Martin Lefebvre, Marco Gonzalez, Maxime Schramme, Remi Dekimpe, Adrian Kneip, Mathieu Xhonneux, Ludovic Moreau, Thibault Pirson |
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| Přispěvatelé: | UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique |
| Rok vydání: | 2021 |
| Předmět: |
Very-large-scale integration
Microcontroller Microcontrollers Power system management Random access memory Very large scale integration Regulation Energy efficiency Monitoring Computer science business.industry Electrical engineering Static random-access memory Power Management Unit Data retention business Voltage Efficient energy use Power (physics) |
| Zdroj: | VLSI Circuits Proceedings of the 2021 Symposium on VLSI Circuits, p. 2 (28/07/2021) |
| Popis: | Ultra-low-power microcontrollers (ULP MCUs) face a performance trade-off between energy-efficient computing during activity periods and low sleep power, associated with limited wake-up time and energy. Adaptive back-biasing in FD-SOI, along with near-threshold operation at ultra-low voltage, has brought significant improvements by dynamically shifting the minimum energy point (MEP) along the frequency axis. This work introduces a highly-integrated 64-MHz ULP Cortex-M4 MCU with 96-kB SRAM in 28nm FD-SOI. A clock and power management unit (CPMU) generates all internal supplies and clocks from a 1.8-V supply, while unified frequency and back-bias regulation (UFBBR) performs PVT compensation. Custom 16-kB ULP SRAMs achieve low read/write access energy, 1.2/0.84pJ/32-bit access respectively, and provide 0.98nW/kB ultra-low-leakage data retention. A low-power biomedical analog front-end enables biopotential monitoring. The MEP is 5.5µW/MHz (8.2µW/MHz including conversion losses). Sleep power is 7.7µW with retention of logic state and 32-kB memory. |
| Databáze: | OpenAIRE |
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