Generation of static tables in embedded memory with dense scheduling
| Autor: | Liliana Cucu-Grosjean, Benot Miramond |
|---|---|
| Přispěvatelé: | Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY), Real time and interoperability (TRIO), INRIA Lorraine, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire Lorrain de Recherche en Informatique et ses Applications (LORIA), Institut National de Recherche en Informatique et en Automatique (Inria)-Université Henri Poincaré - Nancy 1 (UHP)-Université Nancy 2-Institut National Polytechnique de Lorraine (INPL)-Centre National de la Recherche Scientifique (CNRS)-Université Henri Poincaré - Nancy 1 (UHP)-Université Nancy 2-Institut National Polytechnique de Lorraine (INPL)-Centre National de la Recherche Scientifique (CNRS), Miramond, Benoît |
| Jazyk: | angličtina |
| Rok vydání: | 2010 |
| Předmět: |
021103 operations research
Computer science [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Design flow 0211 other engineering and technologies Data compression ratio 02 engineering and technology Dynamic priority scheduling Parallel computing 020202 computer hardware & architecture Scheduling (computing) Embedded software Two-level scheduling 0202 electrical engineering electronic engineering information engineering Software design System on a chip [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Computer Science::Operating Systems ComputingMilieux_MISCELLANEOUS |
| Zdroj: | DASIP 2010 IEEE Proceedings Conference on Design and Architectures for Signal and Image Processing Conference on Design and Architectures for Signal and Image Processing, Oct 2010, France. pp.1 DASIP BASE-Bielefeld Academic Search Engine |
| Popis: | In a real-time context, designing the software relies on insuring deterministic behavior and predictability. With system controlling several sensors and actuators sampled at different rates the scheduling theory associates the notion of Hyperperiod. It is a major factor of complexity whether for scheduling validation (simulation), or for generation of the corresponding tables in the case of pure off-line schedules. This paper presents a compression method of static real-time schedules and a design flow for generating real-time hardware schedulers. The goal is to minimize the size in embedded memory of the scheduling tables defined at compile-time. This method exploits Idle times in multiprocessors systems in order to identify cyclic patterns called dense schedules. When applied to our case studies, the average compression rate of our technique is near 90% of the initial schedules size. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|