GATE ENGINEERING OF DOUBLE GATE In0.53Ga0.47As TUNNEL FET
| Autor: | C S Praveen, Shajimon K John, Ajith Ravindran, Susan Abe |
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| Rok vydání: | 2015 |
| Předmět: | |
| Zdroj: | ICTACT Journal on Microelectronics, Vol 1, Iss 3, Pp 91-95 (2015) |
| ISSN: | 2395-1680 2395-1672 |
| DOI: | 10.21917/ijme.2015.0016 |
| Popis: | Increased power-dissipation in upcoming generation digital systems are limited by supply voltage reductions. For such systems, transistors with lower Subthreshold Slopes are needed. Tunnel Field Effect Transistors (TFET), which works on the principle of band-to-band tunnelling, are supposed to be the possible solution for this problem. TFETs ON-current (ION) is usually very low, with the use of semiconductors with indirect and large bandgap, and high effective mass as silicon, where tunnelling probability is depressed. One solution to this problem is the use of III-V semiconductors like InAs, GaSb, GaAsSb, InxGa1-xAs etc. and structure of gate is another important factor. Double gate instead of a single gate structure will provide improvement in ION. Work function of the gate material also has a great impact. In this paper, a study of the impact of In0.53Ga0.47As channel material, gate structure, work function and high-k dielectric for gate for TFET using Cogenda VTCAD is presented. |
| Databáze: | OpenAIRE |
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