Single-Carrier Phase-Disposition PWM Techniques for Multiple Interleaved Voltage-Source Converter Legs

Autor: Salvador Ceballos, Georgios Konstantinou, Josep Pou, Gabriel J. Capella
Přispěvatelé: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. TIEG-P - Terrassa Industrial Electronics Group -Power, School of Electrical and Electronic Engineering, Electrical Power Systems Integration Lab, Energy Research Institute @ NTU (ERI@N)
Rok vydání: 2018
Předmět:
multilevel converters
Computer science
02 engineering and technology
Electric inductors
Inductor
Pulse width modulation
Harmonic analysis
Interleaving
Multilevel Converters (MMC)
0202 electrical engineering
electronic engineering
information engineering

Electronic engineering
Inductors
Convertidors de corrent elèctric
Voltage source
Electrical and Electronic Engineering
Locomoció
Enginyeria elèctrica [Àrees temàtiques de la UPC]
Sorting
020208 electrical & electronic engineering
Anàlisi harmònica
Feedback loop
Electric current converters
voltage source converters
Control and Systems Engineering
parallel legs
Electrical and electronic engineering [Engineering]
multilevel waveforms
Power system harmonics
Harmonic
Legged locomotion
020201 artificial intelligence & image processing
Inductors elèctrics
Switches
Locomotion
Pulse-width modulation
Zdroj: Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
ISSN: 1557-9948
0278-0046
Popis: Interleaved converter legs are typically modulated with individual carriers per leg and phase-shifted PWM (PS-PWM) as it facilitates current balancing amongst the legs. Phase-disposition PWM (PD-PWM), despite the better harmonic performance, cannot be directly used due to the resulting current imbalance that may damage the converter. This paper addresses the current sharing issue and proposes a single-carrier PD-PWM technique for multiple leg two-level converters based on a hierarchy scheme derived from current sorting algorithms. An extension of the proposed algorithm through a switching state feedback loop, limiting the average switching frequency, is also developed. In both cases, the load current is shared amongst the legs and the high-quality of the output voltages and currents is maintained while the circulating currents amongst the converter legs are kept to a minimum. Simulation results demonstrate the method for multiple interleaved legs as well as its current sharing capabilities for high-power applications. Experimental results from a low-power laboratory prototype validate the operation of the proposed approach.
Databáze: OpenAIRE