Characterizing memory bottlenecks in GPGPU workloads
| Autor: | Vijay Nagarajan, Nigel Topham, Saumay Dublish |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Memory hierarchy Cache coloring Computer science Cache-only memory architecture Memory bandwidth 02 engineering and technology Parallel computing Cache pollution 01 natural sciences 020202 computer hardware & architecture Non-uniform memory access Computer architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Interleaved memory Bandwidth (computing) |
| Zdroj: | Dublish, S, Nagarajan, V & Topham, N 2016, Characterizing memory bottlenecks in GPGPU workloads . in 2016 IEEE International Symposium on Workload Characterization (IISWC) . Institute of Electrical and Electronics Engineers (IEEE), Providence, RI, USA, pp. 1-2, 2016 IEEE International Symposium on Workload Characterization, Providence, United States, 25/09/16 . https://doi.org/10.1109/IISWC.2016.7581287 IISWC |
| DOI: | 10.1109/IISWC.2016.7581287 |
| Popis: | GPUs are often limited by the off-chip memory bandwidth. With the advent of general-purpose computing on GPUs, cache hierarchy has been introduced to filter the bandwidth demand to the off-chip memory. However, the cache hierarchy presents its own bandwidth limitations in sustaining such high levels of memory traffic. In this work, we characterize the bandwidth bottleneck in GPUs present across the memory hierarchy for general-purpose applications. We show that the improvement in performance achieved by mitigating the bandwidth bottleneck in the cache hierarchy can exceed the speedup obtained by a memory system with a baseline cache hierarchy and high bandwidth off-chip memory. We also show that addressing the bandwidth bottleneck in isolation at specific levels can be sub-optimal and can even be counter-productive. Therefore, we show that it is imperative to resolve the bandwidth bottleneck synergistically across different levels of the memory hierarchy. |
| Databáze: | OpenAIRE |
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