A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

Autor: Ming-Yi Lin, Min-Chun Tuan, Tsun-Kuang Chi, Liang-Hung Wang, Wei-Yuan Chiang, Shih-Lun Chen, Patricia Angela R. Abu, Chiung-An Chen
Rok vydání: 2020
Předmět:
Computer Networks and Communications
Computer science
Serial communication
SPI
digital signal process
lcsh:TK7800-8360
02 engineering and technology
Integrated circuit design
Gate count
Gate array
field-programmable gate array (FPGA)
Chip select
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering
electronic engineering
information engineering
Electrical and Electronic Engineering
Field-programmable gate array
business.industry
lcsh:Electronics
020208 electrical & electronic engineering
020206 networking & telecommunications
Chip
Peripheral
communication protocols
Hardware and Architecture
Control and Systems Engineering
Logic analyzer
Signal Processing
Data lines
electronic device measurement and very-large-scale integration (VLSI)
business
CMOS digital integrated circuit
Computer hardware
Zdroj: Electronics, Vol 9, Iss 1509, p 1509 (2020)
Electronics
Volume 9
Issue 9
ISSN: 2079-9292
DOI: 10.3390/electronics9091509
Popis: In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 &mu
m2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 &mu
m CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.
Databáze: OpenAIRE
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