Hardware Architecture for List Successive Cancellation Decoding of Polar Codes
| Autor: | Andreas Burg, Alexios Balatsoukas-Stimming, Warren J. Gross, Alexandre J. Raymond |
|---|---|
| Rok vydání: | 2014 |
| Předmět: |
Very-large-scale integration
Hardware architecture Computer science Error floor very-large-scale integration (VLSI) 020208 electrical & electronic engineering List decoding 020206 networking & telecommunications 02 engineering and technology Sequential decoding Parallel computing polar codes List successive cancellation (SC) decoding 0202 electrical engineering electronic engineering information engineering Electronic engineering Polar Electrical and Electronic Engineering Throughput (business) Decoding methods |
| Zdroj: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2014.2327336 |
| Popis: | This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz. |
| Databáze: | OpenAIRE |
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