Best Practices for Compact Modeling in Verilog-A
| Autor: | Geoffrey Coram, Colin C. McAndrew, Sadayuki Yoshitomi, G.D.J. Smit, Xufeng Wang, Laurence W. Nagel, A. S. Roy, J. Robert Jones, Andries J. Scholten, Jaijeet Roychowdhury, Kiran Kumar Gullapalli |
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| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: |
Computer science
business.industry media_common.quotation_subject Best practice Numerical models Electronic Optical and Magnetic Materials Semiconductor industry Verilog-A Convergence (routing) Electronic engineering Hardware design languages Quality (business) lcsh:Electrical engineering. Electronics. Nuclear engineering Electrical and Electronic Engineering Software engineering business lcsh:TK1-9971 Biotechnology De facto standard media_common |
| Zdroj: | IEEE Journal of the Electron Devices Society, Vol 3, Iss 5, Pp 383-396 (2015) |
| ISSN: | 2168-6734 |
| Popis: | Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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