Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM
| Autor: | Joris Lacord, Campbell Millar, Mukta Singh Parihar, Pascal Fonteneau, Hassan El Dirani, Yong Tae Kim, Sorin Cristoloveanu, Maryline Bawedin, Jean-Charles Barbe, Francisco Gamiz, Noel Rodriguez, Siegfried Karg, Paul Wells, Asen Asenov, Binjie Cheng, Carlos Navarro, M. Duan, Philippe Galy, Cyrille Le Royer, Fikru Adamu-Lema |
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| Přispěvatelé: | University of Granada [Granada], Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), James Watt School of Engineering [Univ Glasgow], University of Glasgow, Synopsys Inc., STMicroelectronics [Crolles] (ST-CROLLES), IBM Research Laboratory [Zurich], IBM Research [Zurich], Surecore, Leeds, Korea Advanced Institute of Science and Technology (KAIST), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), Universidad de Granada = University of Granada (UGR) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Z²-FET Z2-FET 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY eDRAM Semiconductor memories 01 natural sciences fully depleted (FD) 1T-DRAM Capacitorless capacitorless Low-power 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Ground plane Electrical and Electronic Engineering Diffusion (business) [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Silicon-on-insulator 010302 applied physics lifetime Hardware_MEMORYSTRUCTURES business.industry Reading (computer) ground plane Electrical engineering Charge (physics) Feedback effect 021001 nanoscience & nanotechnology Electronic Optical and Magnetic Materials sharp switch Fully depleted (FD) Sharp switch T-Dram Logic gate feedback effect State (computer science) 0210 nano-technology business silicon-on-insulator (SOI) Lifetime Dram |
| Zdroj: | IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2017, 64 (11), pp.4486-4491. ⟨10.1109/TED.2017.2751141⟩ IEEE Transactions on Electron Devices, 2017, 64 (11), pp.4486-4491. ⟨10.1109/TED.2017.2751141⟩ Digibug. Repositorio Institucional de la Universidad de Granada instname |
| ISSN: | 0018-9383 |
| Popis: | This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). DOI: 10.1109/TED.2017.2751141 (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works." The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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