A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Autor:	Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Rok vydání:	2023
Předmět:	low-spot noise bang-bang phase-locked loop (PLL) low jitter quantization noise (QN) Electrical and Electronic Engineering 5G
Zdroj:	IEEE Journal of Solid-State Circuits. 58:634-646
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2022.3228899
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6802fed3b5523c68c56c2837d7ae85bf https://doi.org/10.1109/jssc.2022.3228899 Zobrazit plný text záznamu