Error metrics determination in functionally approximated circuits using SAT solvers

Autor: Sa'ed Abed, Ali A. M. R. Behiry, Imtiaz Ahmad
Jazyk: angličtina
Rok vydání: 2020
Předmět:
Computer and Information Sciences
Adder
Statistical methods
Computer science
media_common.quotation_subject
Computation
Science
02 engineering and technology
Research and Analysis Methods
law.invention
Set (abstract data type)
Electronics Engineering
law
020204 information systems
0202 electrical engineering
electronic engineering
information engineering
Computer Simulation
Mathematical Computing
media_common
Multidisciplinary
Applied Mathematics
Simulation and Modeling
Statistics
Probability Theory
Probability Distribution
Computing Methods
020202 computer hardware & architecture
Monte Carlo method
Logic Circuits
Debugging
Research Design
Electrical network
Physical Sciences
Benchmark (computing)
Mathematical and statistical techniques
Engineering and Technology
Probability distribution
Medicine
Electrical Faults
Boolean satisfiability problem
Algorithm
Algorithms
Mathematics
Electrical Engineering
Research Article
Electrical Circuits
Zdroj: PLoS ONE, Vol 15, Iss 1, p e0227745 (2020)
PLoS ONE
ISSN: 1932-6203
Popis: Approximate computing is an emerging design paradigm that offers trade-offs between output accuracy and computation efforts by exploiting some applications’ intrinsic error resiliency. Computation of error metrics is of paramount importance in approximate circuits to measure the degree of approximation. Most of the existing techniques for evaluating error metrics apply simulations which may not be effective for evaluation of large complex designs because of an immense increase in simulation runtime and a decrease in accuracy. To address these deficiencies, we present a novel methodology that employs SAT (Boolean satisfiability) solvers for fast and accurate determination of error metrics specifically for the calculation of an average-case error and the maximum error rate in functionally approximated circuits. The proposed approach identifies the set of all errors producing assignments to gauge the quality of approximate circuits for real-life applications. Additionally, the proposed approach provides a test generation method to facilitate design choices, and acts as an important guide to debug the approximate circuits to discover and locate the errors. The effectiveness of the approach is demonstrated by evaluating the error metrics of several benchmark-approximated adders of different sizes. Experimental results on benchmark circuits show that the proposed SAT-based methodology accurately determines the maximum error rate and an average-case error within acceptable CPU execution time in one go, and further provides a log of error-generating input assignments.
Databáze: OpenAIRE
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