Design and implementation of SRRC IP generator
| Autor: | Chih Hung Tseng, Jue Hsuan Hsiao, Yi Hua Chen, Pang Fu Liu, Kun Feng Lin |
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| Rok vydání: | 2011 |
| Předmět: |
Adder
Finite impulse response business.industry Computer science Matched filter Parallel computing Raised-cosine filter Logic synthesis Filter (video) VHDL Booth's multiplication algorithm Hardware_ARITHMETICANDLOGICSTRUCTURES Altera Quartus business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Computer hardware Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | 2011 11th International Conference on ITS Telecommunications. |
| DOI: | 10.1109/itst.2011.6060165 |
| Popis: | This work demonstrates the implementation of visual IP generator for Square Root Raised Cosine (SRRC) filter based on Microsoft Visual Studio 2008. The sum of coefficient product terms is the major part in the SRRC filter. In the Visual IP Generator, we proposed a novel algorithm that can translate the sum of coefficient product term on behalf of SRRC filter into the sum of bit shifted term, and then uses Booth Algorithm as well as group reusable to minimize the number of bit shifted term for reducing adder used. The SRRC IP generated from this work is also compiled and simulated in Altera Quartus II and compared with the Altera FIR Compiler synthesized SRRC filter. The comparison results verified our implemented SRRC filter is better than the SRRC filter constructed by Altera build-in IP Code. Our design can be accomplished by three stages: set up SRRC filter parameters, establish the simplified adder tree, and synthesis the VHDL Code. Through these steps, user can save a lot of time and effort in designing and simulation a SRRC filter using VHDL code. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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