Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
| Autor: | Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Salonik Resch, Arvind Sharma, Sachin S. Sapatnekar, Meghna G. Mankalale, Jian-Ping Wang, Ulya R. Karpuzcu |
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| Rok vydání: | 2020 |
| Předmět: |
In-memory computing
lcsh:Computer engineering. Computer hardware Computer science Computation lcsh:TK7885-7895 02 engineering and technology Integrated circuit 01 natural sciences law.invention In-Memory Processing law 0103 physical sciences Limit (music) 0202 electrical engineering electronic engineering information engineering Electronic engineering Parasitic extraction Electrical and Electronic Engineering spin-transfer torque computational random access memory (STT-CRAM) spintronics 010302 applied physics Control reconfiguration 020202 computer hardware & architecture Electronic Optical and Magnetic Materials Noise margin Hardware and Architecture Logic gate |
| Zdroj: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 6, Iss 1, Pp 71-79 (2020) |
| ISSN: | 2329-9231 |
| Popis: | This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations. |
| Databáze: | OpenAIRE |
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