A neuromorphic cortical-layer microchip for spike-based event processing vision systems
| Autor: | A.J. Acosta-Jimenez, R. Serrano-Gotarredona, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco |
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| Přispěvatelé: | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores, Gobierno de España, European Union (UE) |
| Rok vydání: | 2006 |
| Předmět: |
Very-large-scale integration
Spike-based processing Pixel business.industry Computer science Frame (networking) Process (computing) ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION Complex event processing Address Event Representation (AER) Chip Convolution VLSI Neuromorphic engineering High-speed signal processing MOS transistor mismatch Subthreshold circuits Computer vision Bio-inspired systems Artificial intelligence Electrical and Electronic Engineering business Address-event representation (AER) 2-D convolutions |
| Zdroj: | Digital.CSIC. Repositorio Institucional del CSIC instname idUS. Depósito de Investigación de la Universidad de Sevilla |
| Popis: | We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 32 pixels. The convolution processor operates on a pixel array of size 32 32, but can process an input space of up to 128 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second. This work was supported by Spanish Research under Grant TIC2003-08164-C03-01 (SAMANTA) and by the European Union under EU Grant IST-2001-34124 (CAVIAR). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science. |
| Databáze: | OpenAIRE |
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