High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Autor: Hung-Chun Chen, Ming-Hsuan Kao, Yi-Ling Jian, Tsung-Ta Wu, Chang-Hong Shen, Chih-Chao Yang, Chiu-Hao Chen, Chiung-Chih Hsu, Kun-Lin Lin, Jia-Min Shieh, Tung-Ying Hsieh, Yu-Lun Chueh, Jie-Yi Yao, Wei-Sheng Lin, Wen-Hsien Huang
Jazyk: angličtina
Rok vydání: 2017
Předmět:
Zdroj: Scientific Reports
Scientific Reports, Vol 7, Iss 1, Pp 1-11 (2017)
ISSN: 2045-2322
Popis: Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
Databáze: OpenAIRE