Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations
| Autor: | Ali Ahmadi, John Carulli, Ke Huang, Bob Orr, Haralampos-G. Stratigopoulos, Amit Nahar, Yiorgos Makris, Michael F. Pas |
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| Přispěvatelé: | University of Texas at Dallas [Richardson] (UT Dallas), Circuits Intégrés Numériques et Analogiques (CIAN), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), San Diego State University (SDSU), Texas Instruments (TI), entreprise, Department of Bioengineering [Dallas] (University of Texas at Dallas) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Engineering
Semiconductor device fabrication Yield (finance) Production engineering Semiconductor device modeling Process design 02 engineering and technology [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI] 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business.industry 020208 electrical & electronic engineering Process (computing) Statistical model [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering Computer Graphics and Computer-Aided Design Integrated circuit yield [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation 020202 computer hardware & architecture Reliability engineering Yield estimation [SPI.TRON]Engineering Sciences [physics]/Electronics Statistical analysis [INFO.INFO-ES]Computer Science [cs]/Embedded Systems Transceiver business Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36 (12), pp.2120-2133. ⟨10.1109/TCAD.2017.2669861⟩ |
| ISSN: | 0278-0070 |
| DOI: | 10.1109/TCAD.2017.2669861⟩ |
| Popis: | International audience; Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices. |
| Databáze: | OpenAIRE |
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