Fast Decoding ECC for future memories
| Autor: | Marco Sforzin, Marco Ferrari, Christophe Laurent, Alessandro Tomasoni, Sandro Bellini, Paolo Amato |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Block code
Computer science Computer Networks and Communications Phase change memory 020208 electrical & electronic engineering Block codes DRAM Error correction codes Galois fields Nonvolatile memory Electrical and Electronic Engineering NAND gate 02 engineering and technology Parallel computing 020202 computer hardware & architecture 0202 electrical engineering electronic engineering information engineering Error detection and correction BCH code Decoding methods |
| Zdroj: | IEEE journal on selected areas in communications 34 (2016): 2486–2497. doi:10.1109/JSAC.2016.2603698 info:cnr-pdr/source/autori:Amato P.; Bellini S.; Ferrari M.; Laurent C.; Sforzin M.; Tomasoni A./titolo:Fast Decoding ECC for future memories/doi:10.1109%2FJSAC.2016.2603698/rivista:IEEE journal on selected areas in communications (Print)/anno:2016/pagina_da:2486/pagina_a:2497/intervallo_pagine:2486–2497/volume:34 |
| DOI: | 10.1109/JSAC.2016.2603698 |
| Popis: | High performance Storage Class Memories could benefit from a fast decoding Error Correcting Code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents from adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore we propose an architecture for fast decoding of double-and triple-error correcting codes. In our architecture any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular the Error Locator Polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here we describe a gate level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|