Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications
| Autor: | Marcel Kossel, Pedro A. M. Bezerra, Johann W. Kolar, Pier Andrea Francese, T. Morf, Thomas Brunschwiler, Riduan K. Aljameh, Stephan Paredes, Matthias Braendli, Ralph Heller, Florian Krismer |
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| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Thermal electrical characterization
Half-bridge 14 nm technology ANPC CMOS IVR Multi-phase PMIC Stacked transistors 02 engineering and technology Voltage regulator Type (model theory) Topology Inductor 01 natural sciences law.invention law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical measurements Electrical impedance 010302 applied physics Physics Buck converter 020208 electrical & electronic engineering Capacitor lcsh:Electrical engineering. Electronics. Nuclear engineering lcsh:TK1-9971 |
| Zdroj: | IEEE Open Journal of Power Electronics, 1 IEEE Open Journal of Power Electronics, Vol 1, Pp 456-468 (2020) |
| ISSN: | 2644-1314 |
| Popis: | Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB and inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1% at an output power of P out = 640 mW and a switching frequency of f s = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at f s = 50 MHz and P out ∈ [500 mW, 600 mW]; at P out = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs. IEEE Open Journal of Power Electronics, 1 ISSN:2644-1314 |
| Databáze: | OpenAIRE |
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