Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration
| Autor: | P. Ruault, Gong Bo, O. Hinsinger, B. van Schravendijk, D. Winandy, C. Fenouillet-Beranger, D. Galpin, D. Vo-Thanh, S. Lagrasta, Romain Duru, Remi Beneyton, C. Gaumer, J. Mazurier, S. Chhun, N. Chauvet, Bhadri N. Varadarajan, D. Barge, P. Meijer, N. Sun, Daniel Benoit |
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| Rok vydání: | 2015 |
| Předmět: |
010302 applied physics
Very-large-scale integration Materials science business.industry 020209 energy Effective capacitance Oxide Nanotechnology 02 engineering and technology 7. Clean energy 01 natural sciences chemistry.chemical_compound chemistry Low temperature deposition Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Optoelectronics Electrical performance Breakdown voltage business NMOS logic |
| Zdroj: | 2015 IEEE International Electron Devices Meeting (IEDM) |
| Popis: | For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and translates into a 5% decrease for both effective capacitance and delay of FO3 Ring Oscillators in a 14FDSOI technology. In addition, a NMOS breakdown voltage improvement of 3.5V and a decrease in leakage current of 0.7 decade is demonstrated on thick oxide devices. This electrical performance together with the low temperature deposition makes SiCO a very appealing candidate for 3D VLSI in a CoolCube™ integration scheme. |
| Databáze: | OpenAIRE |
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