Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations
| Autor: | M. Mouhdach, Sebastien Thuries, Didier Lattard, G. Cibrario, O. Billoint, K. Azizi-Mourier, Pascal Vivet |
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| Rok vydání: | 2019 |
| Předmět: |
Interconnection
Computer science 020208 electrical & electronic engineering Stacking Process design 02 engineering and technology 020202 computer hardware & architecture Computer architecture Proof of concept Memory architecture 0202 electrical engineering electronic engineering information engineering Granularity Engineering design process Electronic circuit |
| Zdroj: | 2019 International 3D Systems Integration Conference (3DIC) 3DIC |
| DOI: | 10.1109/3dic48104.2019.9058793 |
| Popis: | Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of low granularity of these 3D interconnect elements, this methodology becomes less effective for 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIVs) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment for 3D sequential technology by merging Process Design Kits (PDKs) of different technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing. As a proof of concept, we designed and taped-out a RISC-V processor with logic on memory architecture using LETI CoolCube 28nm FDSOI on top of ST 28nm FDSOI technology. |
| Databáze: | OpenAIRE |
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