Thermoelectric Efficiency of Epitaxial GeSn Alloys for Integrated Si-Based Applications: Assessing the Lattice Thermal Conductivity by Raman Thermometry
| Autor: | Nils von den Driesch, C. L. Manganelli, Marvin Hartwig Zoellner, Toma Stoica, Agnieszka Anna Corley-Wiciak, Giovanni Capellini, Detlev Grützmacher, Davide Spirito, Zoran Ikonic, Dan Buca |
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| Přispěvatelé: | Spirito, Davide, von den Driesch, Nil, Manganelli, Costanza Lucia, Zoellner, Marvin Hartwig, Corley-Wiciak, Agnieszka Anna, Ikonic, Zoran, Stoica, Toma, Grützmacher, Detlev, Buca, Dan, Capellini, Giovanni |
| Rok vydání: | 2021 |
| Předmět: |
Work (thermodynamics)
Materials science business.industry Alloy Energy Engineering and Power Technology Atmospheric temperature range engineering.material Epitaxy symbols.namesake Semiconductor ddc:540 Thermoelectric effect Materials Chemistry Electrochemistry symbols engineering Chemical Engineering (miscellaneous) Optoelectronics Figure of merit Electrical and Electronic Engineering business Raman spectroscopy |
| Zdroj: | ACS applied energy materials 4(7), 7385-7392 (2021). doi:10.1021/acsaem.1c01576 |
| ISSN: | 2574-0962 |
| DOI: | 10.1021/acsaem.1c01576 |
| Popis: | Energy harvesting for Internet of Things applications, comprising sensing, life sciences, wearables, and communications, requires efficient thermoelectric (TE) materials, ideally semiconductors compatible with Si technology. In this work, we investigate the potential of GeSn/Ge layers, a group IV material system, as TE material for low-grade heat conversion. We extract the lattice thermal conductivity, by developing an analytical model based on Raman thermometry and heat transport model, and use it to predict thermoelectric performances. The lattice thermal conductivity decreases from 56 W/(m·K) for Ge to 4 W/(m·K) by increasing the Sn atomic composition to 14%. The bulk cubic Ge0.86Sn0.14 alloy features a TE figure of merit of ZT ∼ 0.4 at 300 K and an impressive 1.04 at 600 K. These values are extremely promising in view of the use of GeSn/Ge layers operating in the typical on-chip temperature range. |
| Databáze: | OpenAIRE |
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