NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories
| Autor: | Ozcan Ozturk, Hamzeh Ahangari, Ihsen Alouani, Smail Niar |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Computer science
Digital storage Reliability (computer networking) Soft errors Cache memory Errors Static noise margin Computer control Systems analysis 02 engineering and technology Parallel computing Read static noise margin (RSNM) Static random access storage SNM 0202 electrical engineering electronic engineering information engineering Electronic engineering Overhead (computing) Static random-access memory Soft error Static random access memory Error correction Hardware_MEMORYSTRUCTURES Technology shift Reliability enhancement 020208 electrical & electronic engineering Radiation hardening Voltage scaling Reliability SRAM 020202 computer hardware & architecture Soft error rate Bit error rate Cache Random errors Error resilience Random access Random access storage Voltage |
| Zdroj: | 2016 Euromicro Conference on Digital System Design (DSD) DSD |
| Popis: | Date of Conference: 31 Aug.-2 Sept. 2016 Conference name: 2016 Euromicro Conference on Digital System Design (DSD) Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance. © 2016 IEEE. |
| Databáze: | OpenAIRE |
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