Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition
| Autor: | Jae-Won Nam, Young-Kyun Cho, Youn Kyu Lee |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
PVT
TK7800-8360 Computer Networks and Communications Hardware_PERFORMANCEANDRELIABILITY SOI process machine learning Hardware and Architecture Control and Systems Engineering Signal Processing FinFET artificial neural network AMS SAR ADC Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Electronics |
| Zdroj: | Electronics, Vol 11, Iss 408, p 408 (2022) Electronics; Volume 11; Issue 3; Pages: 408 |
| ISSN: | 2079-9292 |
| Popis: | An analog and mixed-signal (AMS) circuit that draws on machine learning while using a regression model differs in terms of the design compared to more sophisticated circuit designs. Technology structures that are more advanced than conventional CMOS processes, specifically the fin field-effect transistor (FinFET) and silicon-on-insulator (SOI), have been proposed to provide the higher computation performance required to meet various design specifications. As a result, the latest research on AMS design optimization has enabled enormous resource savings in AMS design procedures but remains limited with regard to reflecting the intended operating conditions in the design parameters. Hereby, we propose what is termed a supervised learning artificial neural network (ANN) as a means by which to define an AMS regression model. This approach allows for rapid searches of complex design dimensions, including variations in performance metrics caused by process–voltage–temperature (PVT) changes. The method also reduces the considerable computation expense compared to that of simulation-program-with-integrated-circuit-emphasis (SPICE) simulations. Hence, the proposed AMS circuit design flow generates highly promising output to meet target requirements while showing an excellent ability to match the design target performance. To verify the potential and promise of our design flow, a successive approximation register analog-to-digital converter (SAR ADC) is designed with a 14 nm process design kit. In order to show the maximum single ADC performance (6-bit∼8-bit resolution and few GS/s conversion speed), we have set three different ADC performance targets. Under all SS/TT/FF corners, ±6.25% supply voltage variation, and temperature variation from −40 ∘C to 80 ∘C, the designed SAR ADC using our proposed AMS circuit optimization flow yields remarkable figure-of-merit energy efficiency (approximately 15 fJ/conversion step). |
| Databáze: | OpenAIRE |
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