Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory
| Autor: | Davide Rossi, Luca Benini, Michael Gautschi |
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| Přispěvatelé: | Gautschi, Michael, Rossi, Davide, Benini, Luca |
| Jazyk: | angličtina |
| Rok vydání: | 2014 |
| Předmět: |
Very-large-scale integration
Multi-core processor Instructions per cycle manycore cluster Hardware_MEMORYSTRUCTURES 28 nm FDSOI business.industry Computer science parallel computing Pipeline (computing) RISC OpenRISC VLSI Set (abstract data type) openrisc Engineering (all) Embedded system Benchmark (computing) IPC processor ultra-low power business Computer hardware Efficient energy use |
| Zdroj: | ACM Great Lakes Symposium on VLSI |
| Popis: | The OpenRISC processor core, featuring a flat pipeline and a low area footprint has been integrated in a multi-core ultra-low power (ULP) cluster with a shared multi-banked memory to exploit parallelism in the near-threshold regime. The micro-architecture has been optimized to support a shared L1 memory and to achieve a high value of instructions per cycle (IPC) per core. The proposed architecture achieves IPC results in the range of 0.88 and 1 in a set of benchmark applications which is an improvement of up to 83% with respect to the original OpenRISC implementation. Implemented in 28nm FDSOI technology, the proposed design achieves 177 MOPS when supplied at 0.6V near-threshold voltage. The energy efficiency at this workload is 90.07 MOPS/mW which is an improvement of 50% with respect to what can be achieved with an OpenRISC cluster based on the original micro-architecture. |
| Databáze: | OpenAIRE |
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