Mapping TSN Traffic Scheduling and Shaping to FPGA-Based Architecture
| Autor: | Michael Stübert Berger, Ying Yan, Zifan Zhou |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Ethernet
General Computer Science Computer science Throughput 02 engineering and technology Scheduling algorithms Scheduling (computing) Hardware 0202 electrical engineering electronic engineering information engineering hardware General Materials Science Architecture Field-programmable gate array Real-time systems Ethernet networks FPGA General Engineering scheduling algorithm 020206 networking & telecommunications 020202 computer hardware & architecture real-time systems Computer architecture Asynchronous communication Bounded function Traffic shaping lcsh:Electrical engineering. Electronics. Nuclear engineering lcsh:TK1-9971 |
| Zdroj: | IEEE Access, Vol 8, Pp 221503-221512 (2020) Zhou, Z, Berger, M S & Yan, Y 2020, ' Mapping TSN Traffic Scheduling and Shaping to FPGA-based Architecture ', IEEE Access, vol. 8, pp. 221503-221512 . https://doi.org/10.1109/ACCESS.2020.3043887 |
| ISSN: | 2169-3536 |
| Popis: | Time-Sensitive Networking (TSN), which evolves from the Ethernet standards, has been developed to ensure deterministic transmission in data networks. Asynchronous Traffic Shaping (ATS) extends the conventional synchronized TSN with an asynchronous scheduler to guarantee a bounded transmitting delay. In this work, we present a Field Programmable Gate Arrays (FPGA) implementation of a TSN scheduling entity, which leverages ATS for the frame forwarding process. We explore the ATS design by function blocks and compare it with a benchmark design utilizing strict-priority scheduling. In terms of operating frequency, our results indicate that strict-priority scheduling performs 1.05% to 9.56% higher maximum frequency than ATS with the same configurations. Regarding resource utilization, ATS consumes 51% to 119% more logic blocks and 51% to 101% more registers than strict-priority scheduling. Based on the synthesis and fitting results from Register-Transfer Level (RTL) simulations, we provide a general vision of designing and implementing considerations of the ATS function. Specifically, we show the influences of the buffer and bus width configuration on the FPGA implementation scale and data rate. |
| Databáze: | OpenAIRE |
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