Accelerating method of moments based package-board 3D parasitic extraction using FPGA
| Autor: | Anant Devi, Kuruvilla Varghese, Maulik Gandhi, Dipanjan Gope |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Computer science
business.industry Clock rate 020206 networking & telecommunications 02 engineering and technology Method of moments (statistics) Condensed Matter Physics Atomic and Molecular Physics and Optics 020202 computer hardware & architecture Electronic Optical and Magnetic Materials Electrical Communication Engineering Parasitic capacitance Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) Ball grid array 0202 electrical engineering electronic engineering information engineering Hardware acceleration Parasitic extraction Electrical and Electronic Engineering Field-programmable gate array business Computer hardware FPGA prototype |
| Zdroj: | Microwave and Optical Technology Letters. 58:776-783 |
| ISSN: | 0895-2477 |
| DOI: | 10.1002/mop.29660 |
| Popis: | In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016 |
| Databáze: | OpenAIRE |
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