Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor
| Autor: | Seungjun Moon, Changhwan Shin, Chankeun Yoon |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Materials science
lcsh:Biotechnology Fin-shaped field-effect-transistor (FinFET) Silicon on insulator 02 engineering and technology Fully-depleted silicon-on-insulator (FDSOI) device lcsh:Chemical technology lcsh:Technology 01 natural sciences Ferroelectric capacitor law.invention law lcsh:TP248.13-248.65 0103 physical sciences MOSFET lcsh:TP1-1185 General Materials Science lcsh:Science 010302 applied physics Full Paper lcsh:T business.industry Hysteresis Transistor General Engineering Window (computing) 021001 nanoscience & nanotechnology lcsh:QC1-999 Electrode Optoelectronics lcsh:Q 0210 nano-technology business lcsh:Physics |
| Zdroj: | Nano Convergence Nano Convergence, Vol 7, Iss 1, Pp 1-7 (2020) |
| ISSN: | 2196-5404 |
| Popis: | In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key knob in designing the devices. It is experimentally observed that the hysteresis window of FE-FDSOI/FE-FinFET is decreased with (i) increasing the area of the ferroelectric capacitor and/or (ii) decreasing the gate area of baseline FET. The way how to control the hysteresis window of FE-FDSOI/FE-FinFET is proposed and discussed in detail. |
| Databáze: | OpenAIRE |
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