Fabrication of p-type silicon nanowires for 3D FETs using focused ion beam
| Autor: | Lucas P. B. Lima, Jose Godoy Filho, Marcos Vinicius Puydinger dos Santos, José Alexandre Diniz |
|---|---|
| Přispěvatelé: | UNIVERSIDADE ESTADUAL DE CAMPINAS |
| Rok vydání: | 2013 |
| Předmět: |
Solar cells
Materials science Gate dielectric Dielectrophoresis Nanowire Silicon on insulator Nanotechnology Junctionless nanowire transistor Células solares Focused ion beam Nanofios Dieletroforese PMOS logic MOSFET Materials Chemistry Artigo original Wafer Electrical and Electronic Engineering Instrumentation Nanowires business.industry Process Chemistry and Technology Surfaces Coatings and Films Electronic Optical and Magnetic Materials Optoelectronics business |
| Zdroj: | Repositório da Produção Científica e Intelectual da Unicamp Universidade Estadual de Campinas (UNICAMP) instacron:UNICAMP |
| ISSN: | 2166-2754 2166-2746 |
| DOI: | 10.1116/1.4823763 |
| Popis: | Agradecimentos: The authors would like to thank CCS and LPD/IFGW staff for device processing and characteri7ation. The work was supported by INCT-Namitec/Fapesp Abstract: A Ga+ focused ion beam (GaFIB) from a FIB/scanning electron microscopy (SEM) dual beam system was used for Si milling and p-type local doping of p+-type silicon nanowires (p+-SiNWs). The resulting p+-SiNWs were then used to create pMOS junctionless nanowire transistor (INT) prototypes for silicon-on-insulator wafer substrates. The electron beam from the FIB/SEM dual beam system was used to deposit SiO2 gate dielectric and Pt source/drain electrodes for JNT transistors. Width, length, and height dimensions of p+-SiNWs were approximately 35 nm, 6 mu m, and 15 nm, respectively, and the JNT gate length was 1 mu m. Finally, photolithography, Al sputtering deposition, and lift-off processing were conducted to define the Al gate electrode and contacts on Pt source/drain electrodes. Energy dispersive x-ray spectroscopy measurements were taken to confirm the surface composition of p+-SiNWs and Ga doping. Drain-source current (I-DS) versus drain-source voltage (V-DS) measurements of JNT transistors indicated that the device is working like a JNT device (gated resistor). The authors noted high resistance on Al/Pt source and drain electrodes, which leads to distortions on Ins versus V-DS curves as non-ohmic electrical contact for low V-DS signal. However, these distortions can be reduced with a longer contact sintering process or by increased p+-SiNW doping. Our conclusions indicate that utilizing a GaFIB/SEM dual beam system for Si milling, Ga doping, and SiO2 and Pt depositions can be a favorable alternative for fabricating junctionless devices based on p+-SiNWs FUNDAÇÃO DE AMPARO À PESQUISA DO ESTADO DE SÃO PAULO - FAPESP Fechado |
| Databáze: | OpenAIRE |
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