Lower power by voltage stacking
| Autor: | Hamed Fatemi, Jose Pineda de Gyvez, Ajay Kapoor, Kristof Blutman, Jacinto Garcia Martinez |
|---|---|
| Přispěvatelé: | Electronic Systems |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Engineering
Microcontroller Stacked circuits business.industry 020208 electrical & electronic engineering Electrical engineering Stacking Charge recycling 02 engineering and technology Logic level Voltage regulator Hardware_PERFORMANCEANDRELIABILITY Chip 020202 computer hardware & architecture Power (physics) Low power design Level shifter 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_INTEGRATEDCIRCUITS business Electrical efficiency Voltage |
| Zdroj: | Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas, 1-5 STARTPAGE=1;ENDPAGE=5;TITLE=Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, 5-9 June 2016, Austin, Texas DAC |
| DOI: | 10.1145/2897937.2898041 |
| Popis: | Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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