Fine-grain analysis of the parameters involved in aging of digital circuits
| Autor: | Olivier Heron, Chiara Sandionigi, Boukary Ouattara |
|---|---|
| Přispěvatelé: | Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)) |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Timing failures
Engineering Systems analysis 02 engineering and technology Integrated circuit 01 natural sciences Bottleneck law.invention [SPI]Engineering Sciences [physics] Reliability (semiconductor) law 0103 physical sciences Timing circuits 0202 electrical engineering electronic engineering information engineering Electronic engineering Register-transfer level 010302 applied physics Digital electronics business.industry Mixed-signal integrated circuit Digital circuits Fine-grain analysis Circuit extraction 020202 computer hardware & architecture Reliability engineering business Electric network analysis Design time Asynchronous circuit |
| Zdroj: | 2016 IEEE 22nd International Symposium on Testing and Robust System Design (IOLTS) Testing and Robust System Design (IOLTS), Jul 2016, Sant Feliu de Guixols, Spain. pp.51-53, ⟨10.1109/IOLTS.2016.7604671⟩ IOLTS |
| Popis: | Conference of 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 ; Conference Date: 4 July 2016 Through 6 July 2016; Conference Code:124500; International audience; Integrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits. |
| Databáze: | OpenAIRE |
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