| Autor: |
Kang L. Wang, Sudhakar Pamarti, Di Wu, Puneet Gupta, Albert Lee, Seyed Armin Razavi, Jiyue Yang |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
ESSCIRC |
| Popis: |
In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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