A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC
| Autor: | Haralampos-G. Stratigopoulos, Rshdee Alhakim, Matthieu Dubois, Manuel J. Barragan, Neha Bhargava, Herve Le Gall, Ankur Bal, Salvador Mir |
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| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Circuits Intégrés Numériques et Analogiques (CIAN), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Pyxalis (FRANCE), STMicroelectronics, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]) |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Engineering
Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Delta-sigma modulation [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI] Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering System on a chip Electrical and Electronic Engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Bitstream ComputingMilieux_MISCELLANEOUS business.industry Dynamic range 020208 electrical & electronic engineering [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation 020202 computer hardware & architecture [SPI.TRON]Engineering Sciences [physics]/Electronics CMOS Built-in self-test [INFO.INFO-ES]Computer Science [cs]/Embedded Systems business 18-bit Communication channel |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2016, ⟨10.1109/TCSI.2016.2602387⟩ IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, ⟨10.1109/TCSI.2016.2602387⟩ |
| ISSN: | 1549-8328 1558-0806 |
| Popis: | This paper proposes a fully-digital BIST architecture for the dynamic test of $\Sigma\Delta$ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the $\Sigma\Delta$ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio $\Sigma\Delta$ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test. |
| Databáze: | OpenAIRE |
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